1. Field of the Invention
The present invention relates to a semiconductor device having a memory circuit, and particularly to a semiconductor memory device having a larger internal address space than an external address space.
2. Description of the Prior Art
With the advance of semiconductor device technology a large capacity memory can now be formed on a single semiconductor chip. Such a memory with a large capacity has a large address space, so that a long address must be applied thereto. For instance, an external address consisting of 16 bits has to be used to access a 64K.times.1 bit memory. For a 4K word memory (8 bits/word), 12 bits are required as an external address applied to an external address input port of the memory. These large capacity memories can not be directly accessed by a short external address (e.g. 8-bit address or 10-bit address). In the prior art, therefore, a central processing unit (CPU) device which generates only a short address could not be directly coupled to the large capacity memory device via an external address bus.
To access the large capacity memory device by using a CPU device with a short CPU address, a peripheral device to expand the CPU address must be put between the memory device and the CPU device. However, such peripheral device requires a complex hardware circuit, and control of the interface between the CPU device and the memory device becomes difficult. Further, when a plurality of memory devices are employed, each of which has the same address space as the CPU address space, device selection becomes complex in addition to complexity of the system structure.
To avoid these defects, an overlay technology has been proposed. This technology is effective to access a large memory capacity by means of a short CPU address space. However, according to the overlay system, a part of memory corresponding to the CPU address space must be firstly loaded to a rewritable memory device, and thereafter the CPU device has to read out the loaded information from the rewritable memory device. Therefore, the technology has the disadvantage that a memory access speed is very slow.
Furthermore, the large capacity memory contains in general a plurality of application programs or operating systems in arbitrary address spaces. These address spaces are not fixed but variable. In the prior art addressing, an upper address portion is used to designate a start location of one of the memory blocks, and a lower address portion is used to designate each location in the designated memory block. It should be noted that the large capacity memory is divided into memory blocks with a constant address space. However, as described above, since the address space assigned to each of the application programs or operating systems is not fixed but variable, each start location does not correspond to start locations of the memory blocks. Therefore, in order to designate the start location of the application program or the operating system, a complex address operation is required.
An object of the present invention is to provide a semiconductor device having a memory circuit which can be accessed by an external address which is shorter than an internal address of the semiconductor device.
Another object of the present invention is to provide a semiconductor memory device having a larger internal address space than an external address space.
Still another object of the present invention is to provide a semiconductor memory device which can be easily coupled to a CPU device whose address space is smaller than that of the memory device.
Still another object of the present invention is to provide a memory device containing a plurality of programs or informations stored in arbitrary address spaces, each address space being accessed by means of an easy address operation.